Senior Foundry Interface Design Engineer

Description:

Our team vision is a continuing desire to develop your skills working in an inclusive diverse environment of multicultural Teams across worldwide geographies! Enabling the creative career path you deserve with a collaborative environment, and groundbreaking technology while rapidly growing your abilities.

In HBM DEG (High Bandwidth Memory, DRAM Engineering Group), we innovate and integrate end-to-end groundbreaking front-end and backend processes with groundbreaking design, debugging various tests, and qualification techniques to develop the lowest power per bit solutions to improve customer experience in the field of ML (Machine Learning) and AI (Artificial Intelligence). The success of a sophisticated product such as HBM relies vastly on vertical integration and the various engineering working in unison. To provide greater detail, our HBM technology pertains to stacking numbers of DRAM chips along with a logic chip within one package through an assembly technology called TSV (Through Silicon Via). This greatly increases the memory density in a package, while allowing very high-speed signal transmission. Furthermore, "high bandwidth"; is an outstanding memory design area where custom gate-level design and RTL style logic design are blended into the same product, and most of the DDR or LPDDR design is based on the gate-level design only. Lastly, verification and testing (validation) of HBM is the most ambitious due to the total size of the design and complexity of the functions, and in addition to craft, many innovations are needed for verification and validation of the HBM product, thereby making it uniquely exciting.

Responsibilities include but are not limited to

• Focused, self-motivated semiconductor foundry interface engineer providing strategic and technical leadership across the semiconductor industry involving wafer foundries and fabless design houses.
• Use foundry technology process design kits (PDKs) of advanced FinFET and GAA nodes to come up with design guidelines for power/performance optimization.
• Study and analyze Foundry Technology to provide guidelines to design team to improve power/performance/area and reliability.
• Participate in new architecture development for upcoming and future HBM base Die design through Design Technology Co-optimization involving std cells and BEOL options.
• Define Reliability specifications for DRAM and Base Die through cross-functional collaboration to meet the product needs.
• Use statistical computation/ modeling/scripting tools for data analysis.
• Engage with Customers to support issues with current HBM architectures and identify opportunities to innovate on future HBM solutions.
• Yield and reliability analysis, process flow and integration development, product design, and testing optimization to accelerate advanced CMOS technology qualification and mass production ramp-up.
• Pathfinding to explore new architectures for future HBM products and make recommendations after performing a highly technical feasibility analysis.

Qualifications:

• BSEE or greater
• 5+ years of experience technically contributing in the relevant Design/Technology engineering roles.
• Experience working with Foundry Technology PDKs preferably advanced FinFET nodes.
• Experience with EDA tools and design automation etc. with experience in CMOS circuit design. Familiarity with the fundamental concepts associated with parasitic extraction, physical verification, circuit simulation, and reliability verification.
• Understanding of compact device models and aging models is a plus.
• Solid experience in automation using Python or equivalent scripting language is highly encouraged.
• Good understanding of Process Technology and device physics of advanced CMOS device architecture (FinFET and GAA).
• Good verbal and written communication skills with the ability to effectively synthesize and convey complex technical concepts to other partners and leadership.
• Strong track record of innovation and problem-solving in high-performance memory development